PIC16F87 datasheet(94/230 Pages) MICROCHIP

94 / 230 page

PIC16F87/88

DS30487D-page 94

 2002-2013 Microchip Technology Inc.

An SSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF, must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. Flag bit, SSPIF, is set on the falling edge of

the ninth clock pulse.

As a slave transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the data transfer is complete. When the ACK is latched

by the slave device, the slave logic is reset (resets

SSPSTAT register) and the slave device then monitors

for another occurrence of the Start bit. If the SDA line

was low (ACK), the transmit data must be loaded into

the SSPBUF register which also loads the SSPSR

by setting bit CKP.

TABLE 10-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

FIGURE 10-6:

I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

FIGURE 10-7:

I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Status Bits as Data

Transfer is Received

SSPSR

 SSPBUF

Generate ACK Pulse

Set SSPIF Bit

(SSP Interrupt Occurs if Enabled)

SSPOV

Yes

Note 1:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W = 0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

ACK

Transmitting Data

R/W = 1

Receiving Address

5678

123

Cleared in software

SSPBUF is written in software

From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

Data is

sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

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