LPC810M021FN8 datasheet(90/313 Pages) NXP

90 / 313 page

UM10601

All information provided in this document is subject to legal disclaimers.

Preliminary user manual

Rev. 1.0 — 7 November 2012

90 of 313

NXP Semiconductors

UM10601

Chapter 8: LPC800 Pin interrupts/pattern match engine

8.6.9 Pin interrupt falling edge register

This register contains ones for pin interrupts selected in the PINTSELn registers (see

Section 4.6.27) on which a falling edge has been detected. Writing ones to this register

clears falling edge detection. Ones in this register assert an interrupt request for pins that

are enabled for falling-edge interrupts. All edges are detected for all pins selected by the

PINTSELn registers, regardless of whether they are interrupt-enabled.

8.6.10 Pin interrupt status register

Reading this register returns ones for pin interrupts that are currently requesting an

interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones

to this register clears both rising- and falling-edge detection for the pin. For level-sensitive

pins, writing ones inverts the corresponding bit in the Active level register, thus switching

the active level on the pin.

8.6.11 Pattern Match Interrupt Control Register

The pattern match control register contains one bit to select pattern-match interrupt

generation (as opposed to pin interrupts which share the same interrupt request lines),

and another to enable the RXEV output to the cpu. This register also allows the current

state of any pattern matches to be read.

If the pattern match feature is not used (either for interrupt generation or for RXEV

assertion) the two LSB’s of this register should be left at 0b00 to conserve power.

Table 88.

Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description

Bit

Symbol Description

Reset

value

Access

7:0

FDET

Falling edge detect. Bit n detects the falling edge of the pin

selected in PINTSELn.

Read 0: No falling edge has been detected on this pin since

Reset or the last time a one was written to this bit.

Write 0: no operation.

Read 1: a falling edge has been detected since Reset or the

last time a one was written to this bit.

Write 1: clear falling edge detection for this pin.

0R/W

31:8

Reserved.

Table 89.

Pin interrupt status register (IST, address 0xA000 4024) bit description

Bit

Symbol Description

Reset

value

Access

7:0

PSTAT

Pin interrupt status. Bit n returns the status, clears the edge

interrupt, or inverts the active level of the pin selected in

PINTSELn.

Read 0: interrupt is not being requested for this interrupt pin.

Write 0: no operation.

Read 1: interrupt is being requested for this interrupt pin.

Write 1 (edge-sensitive): clear rising- and falling-edge

detection for this pin.

Write 1 (level-sensitive): switch the active level for this pin (in

the IENF register).

0R/W

31:8

Reserved.

LPC810M021FN8 bảng dữ liệu(PDF) 90 Page - NXP Semiconductors

LPC810M021FN8 bảng dữ liệu(HTML) 90 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL