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LPC810M021FN8 bảng dữ liệu(HTML) 29 Page - NXP Semiconductors |
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29 / 313 page  UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Preliminary user manual Rev. 1.0 — 7 November 2012 29 of 313 NXP Semiconductors UM10601 Chapter 4: LPC800 System configuration (SYSCON) 4.6.19 USART fractional generator multiplier value register All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider: U_PCLK = UARTCLKDIV/(1 + MULT/DIV). UARTCLKDIV is the USART clock configured in the UARTCLKDIV register. The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block: 1. The DIV denominator of the fractional divider value is programmed in the UARTFRGDIV register. See Table 23. 2. The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate. See also: Section 15.3.1 “Configure the USART clock and baud rate” Section 15.7.1 “Clocking and Baud rates” 4.6.20 External trace buffer command register <tbd> Table 23. USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description Bit Symbol Description Reset value 7:0 DIV Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0 31:8 - Reserved - Table 24. USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description Bit Symbol Description Reset value 7:0 MULT Numerator of the fractional divider. MULT is equal to the programmed value. 0 31:8 - Reserved - Table 25. External trace buffer command register (EXTTRACECMD, address 0x4004 80FC) bit description Bit Symbol Description Reset value 0 START Trace start command <tbd> 0 1 STOP Trace stop command <tbd> 0 31:2 - Reserved 0 |
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