LPC810M021FN8 datasheet(47/313 Pages) NXP

47 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

47 of 313

NXP Semiconductors

UM10601

Chapter 5: LPC800 Reduced power modes and Power Management

5.7.2 Reduced power modes and WWDT lock features

The WWDT clock select lock feature influences the power consumption in any of the

power modes because locking the WWDT clock source forces the selected WWDT clock

source to be on independently of the Deep-sleep and Power-down mode software

configuration through the PDSLEEPCFG register. For details see Section 12.5.3 “Using

the WWDT lock features”.

If the part uses Deep-sleep mode with the WWDT running, the watchdog oscillator is the

preferred clock source as it minimizes power consumption. If the clock source is not

locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register.

Alternatively, the IRC may be selected and locked in WWDT MOD register, which forces

the IRC on during Deep-sleep mode.

If the part uses Power-down mode with the WWDT running, the watchdog oscillator must

be selected as the clock source. If the clock source is not locked, the watchdog oscillator

must be powered by using the PDSLEEPCFG register. Do not lock the clock source with

the IRC selected.

5.7.3 Active mode

In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,

and peripherals are clocked by the system clock or a dedicated peripheral clock.

The chip is in Active mode after reset and the default power configuration is determined

by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power

configuration can be changed during run time.

5.7.3.1 Power configuration in Active mode

Power consumption in Active mode is determined by the following configuration choices:

• The SYSAHBCLKCTRL register controls which memories and peripherals are

running (Table 18).

• The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and

the flash block) can be controlled at any time individually through the PDRUNCFG

bit description”).

• The clock source for the system clock can be selected from the IRC (default), the

system oscillator, or the watchdog oscillator (see Figure 3 and related registers).

• The system clock frequency can be selected by the SYSPLLCTRL (Table 8) and the

SYSAHBCLKDIV register (Table 17).

• The USART and CLKOUT use individual peripheral clocks with their own clock

dividers. The peripheral clocks can be shut down through the corresponding clock

divider registers.

5.7.4 Sleep mode

In Sleep mode, the system clock to the ARM Cortex-M0+ core is stopped and execution of

instructions is suspended until either a reset or an interrupt occurs.

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