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SPEAR1340 bảng dữ liệu(PDF) 168 Page - STMicroelectronics

tên linh kiện SPEAR1340
Giải thích chi tiết về linh kiện  Dual-core Cortex A9 HMI embedded MPU
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SPEAR1340 bảng dữ liệu(HTML) 168 Page - STMicroelectronics

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Timing characteristics
SPEAr1340
168/200
Doc ID 023063 Rev 4
5.8
GPIO/XGPIO timing characteristics
For edge-sensitive signals, the interrupt line is sampled by flip flops clocked by PCLK for
GPIOs and HCLK for XGPIOs, the APB and AHB clocks, normally running at 83 MHz and
166 MHz respectively.
The minimum pulse width required for interrupt detection on signal edge is:
3*TPCLK (36 ns at 83 MHz) for GPIO
3*THCLK (18 ns at 166 MHz) for XGPIO
5.9
I2C timing characteristics
The timing of high and low level of SCL (TSCLHigh and TSCLLow) are programmable.
Figure 31.
I2C timing waveform
TCLKlow
MAC_MDC pulse width low
60
ns
Ts
Setup time for MDIO input
30
ns
Th
Hold time for MDIO input
0
ns
1.
When MDIO is used as output, the data is launched on the falling edge of the clock as shown in Figure 30.
Table 78.
MAC_MDC/MAC_MDIO timing characteristics (continued)
Symbol
Description
Min
Max
Unit
I2Cx_SCL
I2Cx_SDA
tSCLHigh
tSU-STA
tHD-STA
tSU-DAT
tSU-STO
tHD-STO
tSCLLow



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