SPEAR1340 datasheet(15/200 Pages) STMICROELECTRONICS

15 / 200 page

SPEAr1340

Device functions

Doc ID 023063 Rev 4

15/200

2.10

PCI Express controller (PCIe)

The PCI Express core incorporates a dual-mode (DM) core which can implement a PCIe

interface for a PCIe Root Complex (RC) or Endpoint (EP). The dual-mode core can operate

in EP or RC port modes, depending on value written in a register during PCIe configuration.

PCIe is compliant with the PCI Express Base 2.0 specification, but it is also compliant with

the PCIe 1.1 specification.

The core features a proprietary user-configurable and high-performance application

interface for generating and receiving PCIe traffic. It is available with standard AMBA 3 AXI

interfaces.

Typical applications for a PCI Express device built with the DM core include:

●

Motherboard components for desktop and mobile computers

●

Graphics devices

●

Add-in cards for desktop and mobile computers

●

Components and add-in cards in server applications

●

Embedded applications

●

Data communications equipment

●

Telecommunications equipment

●

Storage devices

●

Wireless devices

●

Other applications

The DM core in EP mode supports PCI Express Legacy Endpoint devices. However, the

application must ensure that the device obeys the Legacy Endpoint device rules defined in

the PCI Express Base 2.0 specification.

Note:

The core is not intended for use in a root complex integrated endpoint.

Main features (common to both EP and RC mode of the DM cores):

●

Support for all non-optional features and some optional features defined in the PCI

Express Base 2.0 specification.

●

Ultra low transmit and receive latency

●

Support a max payload size of 256 bytes

●

4 KB maximum request size

●

Very high accessible bandwidth

●

Support for both Gen1 (at 125 MHz) and Gen2 (at 250 MHz) operation

●

2.5 Gbps (Gen1) or 5.0 Gbps (gen2) Lane (x1)

●

Automatic lane reversal as specified in the PCI Express 2.0 specification (transmit and

receive)

●

Polarity inversion on receive

●

Multiple virtual channels (VCs) (maximum of 2)

●

Multiple traffic classes (TCs)

●

ECRC generation and checking

●

PCI Express beacon and wake-up mechanism

SPEAR1340 bảng dữ liệu(PDF) 15 Page - STMicroelectronics

SPEAR1340 bảng dữ liệu(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL