L99PM62XP datasheet(22/98 Pages) STMICROELECTRONICS

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Description

L99PM62XP

22/98

Doc ID 16363 Rev 3

After power-on or standby mode, the watchdog is started with a long open window (65 ms

nominal). The long open window allows the micro controller to run its own setup and then to

trigger the watchdog via the SPI. The trigger is processed when the CSN input becomes

HIGH after the transmission of the SPI word.

Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window

watchdog (the timing is programmable by SPI). Subsequently, the micro controller has to

serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer

Figure 27). A correct watchdog trigger signal is immediately start the next cycle.

After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. If

subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off

and the device goes into VBAT standby mode until a wakeup occurs.

In case of a watchdog failure, the outputs (RELx, OUTx, V2) are switched off and the device

enters fail-safe mode (i. e. all control registers are set to default values except the ‘OUT3

control bit’).

The following diagrams illustrate the watchdog behavior of the L99PM62. The diagrams are

split into 3 parts. First diagram shows the functional behavior of the watchdog without any

error. The second diagram covers the behavior covering all the error conditions, which can

affect the watchdog behavior. Third diagram shows the transition in and out of Flash mode.

All 3 diagrams can be overlapped to get all the possible state transitions under all

circumstances. For a better readability, they were split in normal operating, operating with

errors and Flash mode.

Figure 9.

Watchdog in normal operating mode (no errors)

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