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ST10F280 bảng dữ liệu(PDF) 196 Page - STMicroelectronics

tên linh kiện ST10F280
Giải thích chi tiết về linh kiện  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST10F280 bảng dữ liệu(HTML) 196 Page - STMicroelectronics

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Special function register overview
ST10F280
196/239
Doc ID 8673 Rev. 3
19.2
System configuration registers
The ST10F280 has registers used for different configuration of the overall system. These
registers are described below.
SYSCON
Address:
0xFF12h / 89h SFR
Reset:
0x0XX0h
Type:
R/W
Note:
Register SYSCON cannot be changed after execution of the EINIT instruction.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STKSZ
XPEN
R/W
R/W
R/W
R/W(1)
1.
These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset
sequence.
R/W(1)
R/W
R/W(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XPER-SHARE XBUS Peripheral Share Mode Control
0: External accesses to XBUS peripherals are disabled
1: XBUS peripherals are accessible via the external bus during hold mode
VISIBLE Visible Mode Control
0: Accesses to XBUS peripherals are done internally
1: XBUS peripheral accesses are made visible on the external pins
XPEN XBUS Peripheral Enable bit
0: Accesses to the on-chip X-Peripherals and XRAM are disabled
1: The on-chip X-Peripherals are enabled.
BDRSTEN Bidirectional Reset Enable
0: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)
1: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset
sequence.
OWDDIS Oscillator Watchdog Disable Control
0: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors
XTAL1 activity. If there is no activity on XTAL1 for at least 1
μs, the CPU clock is
switched automatically to PLL’s base frequency (2 to 10MHz).
1: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1
signal. The PLL is turned off to reduce power supply current.
PWDCFG Power Down Mode Configuration Control
0: Power Down Mode can only be entered during PWRDN instruction execution if NMI
pin is low, otherwise the instruction has no effect. Exit power down only with reset.
1: Power Down Mode can only be entered during PWRDN instruction execution if all
enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode
can be done by asserting one enabled EXxIN pin or with external reset.



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