ST10F280_12 datasheet(159/239 Pages) STMICROELECTRONICS

159 / 239 page

ST10F280

CAN modules

Doc ID 8673 Rev. 3

159/239

Control / Status Register

Address:

0xEF00h / 0xEE00h XReg

Reset:

0xXX01h

Type:

R, R/W

BOFF

EWRN

RXOK TXOK

LEC

TST

CCE

EIE

SIE

INIT

R/W

INIT Initialization

1: Software initialization of the CAN controller. While init is set, all message transfers are

stopped. Setting init does not change the configuration registers and does not stop

transmission or reception of a message in progress. The INIT bit is also set by hardware,

following a busoff condition; the CPU then needs to reset INIT to start the bus recovery

sequence.

0: Disable software initialization of the CAN controller; on INI completion, the CAN waits

for 11 consecutive recessive bit before taking part in bus activities.

IE Interrupt Enable Does not affect status updates.

1: Global interrupt enable from CAN module.

0: Global interrupt disable from CAN module.

SIE Status Change Interrupt Enable

1: Enables interrupt generation when a message transfer (reception or transmision is

successfully completed) or CAN bus error is detected and registered in LEC is the status

partition.

0: Disable status change interrupt.

EIE Error Interrupt Enable

1: Enables interrupt generation on a change of bit BOFF or EWARN in the status partition.

0: Disable error interrupt.

CCE Configuration Change Enable

1: Allows CPU access to the bit timing register

0: Disables CPU access to the bit timing register

TST Test Mode (Bit 7)

Make sure that bit 7 is cleared when writing to the Control Register. Writing a 1 during

normal operation may lead erroneous device behaviour.

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