STA369BW datasheet(44/88 Pages) STMICROELECTRONICS

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STA369BW

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Doc ID 022033 Rev 1

7.5.8

Soft-volume update enable

7.6

Configuration register F (addr 0x05)

7.6.1

Output configuration

Note:

To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

Table 42.

Soft-volume update enable

Bit

R/W

RST

Name

Description

7R/W

SVE

1: Volume adjustments ramp according to SVR settings

0: Volume adjustments occur immediately

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

OCFG1

OCFG0

Table 43.

Output configuration

Bit

R/W

RST

Name

Description

R/W

OCFG0

Selects the output configuration

R/W

OCFG1

Table 44.

Output configuration engine selection

OCFG[1:0]

Output configuration

Config pin

2-channel (full-bridge) power, 2-channel data-out:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

LineOut1

→ 3A/3B

LineOut2

→ 4A/4B

Line Out Configuration determined by LOC register

2(half-bridge).1(full-bridge) on-board power:

→ 1A

Binary 0 °

→ 1B

Binary 90°

3A/3B

→ 2A/2B Binary 45°

1A/B

→ 3A/B

Binary 0°

2A/B

→ 4A/B

Binary 90°

2-channel (full-bridge) power, 1-channel FFX:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

3A/3B

→ 3A/3B

EAPDEXT and TWARNEXT Active

1-channel mono parallel:

→ 1A/1B

w/ C3BO 45°

→ 2A/2B

w/ C3BO 45°

1A/1B

→ 3A/3B

2A/2B

→ 4A/4B

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