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STA369BW bảng dữ liệu(PDF) 80 Page - STMicroelectronics

tên linh kiện STA369BW
Giải thích chi tiết về linh kiện  Sound Terminal® 2.1-channel high-efficiency digital audio system
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STA369BW bảng dữ liệu(HTML) 80 Page - STMicroelectronics

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Register description
STA369BW
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Doc ID 022033 Rev 1
In this case the user can decide, for each filter stage, the right coefficients range. Note that
for a given biquad, the same range will be applied to left and right (channel 1 and channel
2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1)
range unchanged.
7.24
Miscellaneous registers (address 0x4B, 0x4C)
7.24.1
Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA369BW, by default, the power-down pin and I2C power-down act on mute
commands to perform the fadeout. This default can be changed so that the fadeout can be
started using the master volume. The RPDNEN bit, when set, activates this feature.
7.24.2
Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B,
bit D6)
Following the description in Section 7.22, this bit, when set, enables the noise-shaping
technique on the DC cutoff filter. Channels 1 and 2 share the same settings.
7.24.3
Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)
A fadeout procedure is started in the STA369BW once the PWDN function is enabled.
Independently from the fadeout time, after 13 million clock cycles (PLL internal frequency)
the bridge is put in power-down (tristate mode). There is also the possibility to change this
behavior so that the power bridge will be switched off immediately after the PWDN pin is tied
to ground, without waiting for the 13 million clock cycles. The BRIDGOFF bit, when set,
activates this function. Obviously the immediate power-down will generate a pop noise at
the output, therefore this procedure must be used only in case pop noise is not relevant in
the application. Note that this feature works only for hardware PWDN assertion and not for a
power-down applied through the I2C interface. Refer to Section 7.24.5 in order to program a
different number of clock cycles.
D7
D6
D5
D4
D3
D2
D1
D0
RPDNEN
NSHHPEN
BRIDGOFF Reserved
Reserved
CPWMEN
Reserved
Reserved
0
0
00
01
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
Reserved
PNDLSL[2] PNDLSL[1] PNDLSL[0] Reserved
Reserved
00
0
0
0
0
0
0



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