EDJ2104BASE datasheet(1/148 Pages) ELPIDA

tên linh kiện	EDJ2104BASE

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Document No. E1505E20 (Ver. 2.0)

Date Published November 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2009

PRELIMINARY DATA SHEET

2G bits DDR3 SDRAM

EDJ2104BASE (512M words

× 4 bits)

EDJ2108BASE (256M words

× 8 bits)

Specifications

• Density: 2G bits

• Organization

 64M words × 4 bits × 8 banks (EDJ2104BASE)

 32M words × 8 bits × 8 banks (EDJ2108BASE)

• Package

 78-ball FBGA

 Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.5V ± 0.075V

• Data rate

 1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)

• 1KB page size

 Row address: A0 to A14

 Column address: A0 to A9, A11 (EDJ2104BASE)

A0 to A9 (EDJ2108BASE)

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

 Sequential (8, 4 with BC)

 Interleave (8, 4 with BC)

• /CAS Latency (CL): 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

 Average refresh period

7.8

µs at 0°C ≤ TC ≤ +85°C

3.9

µs at +85°C < TC ≤ +95°C

• Operating case temperature range

 TC = 0°C to +95°C

Features

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

 Synchronous ODT

 Dynamic ODT

 Asynchronous ODT

• Multi Purpose Register (MPR) for temperature read

out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

• SRT range:

 Normal/extended

• Programmable Output driver impedance control

Số phần tương tự - EDJ2104BASE

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Elpida Memory	EDJ2104BDBG	447Kb / 30P	Differential clock inputs
	EDJ2104BDBG-8C-F	447Kb / 30P	Differential clock inputs
	EDJ2104BDBG-AE-F	447Kb / 30P	Differential clock inputs
	EDJ2104BDBG-DJ-F	447Kb / 30P	Differential clock inputs
	EDJ2104BDBG-GN-F	447Kb / 30P	Differential clock inputs

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nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Elpida Memory	EDE2116ABSE	642Kb / 81P	2G bits DDR2 SDRAM
	EDJ1104BDSE	1Mb / 147P	1G bits DDR3 SDRAM
	EDE2104ABSE	782Kb / 81P	2G bits DDR2 SDRAM
	EDE2116AEBG	528Kb / 73P	2G bits DDR2 SDRAM
	EDJ1104BFBG	1Mb / 147P	1G bits DDR3 SDRAM
	EDJ5304BASE	1Mb / 130P	512M bits DDR3 SDRAM
	E1712E60	404Kb / 33P	2G bits DDR3 SDRAM
	E1750E31	606Kb / 32P	2G bits DDR3L SDRAM
	EDE2108AEBG-8E-F	498Kb / 73P	2G bits DDR2 SDRAM
	EDE2116AEBG-8E-F	528Kb / 73P	2G bits DDR2 SDRAM

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