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EDJ2104BASE bảng dữ liệu(PDF) 79 Page - Elpida Memory

tên linh kiện EDJ2104BASE
Giải thích chi tiết về linh kiện  2G bits DDR3 SDRAM
PDF  148 Pages
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EDJ2104BASE, EDJ2108BASE
Preliminary Data Sheet E1505E20 (Ver. 2.0)
79
DDR3 SDRAM Mode Register 2 [MR2]
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write
latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on
BA0, while con-trolling the states of address pins according to the table below.
Address field
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA2
BA0
A12
0*1
Mode register 2
0*
1
0*
1
2
PASR*
SRT
Rtt_WR*
2
0
1
ASR
CWL
A13
Notes: 1. BA2, A8, and A11 to A14 are RFU and must be programmed to 0 during MRS.
2. The Rtt_WR value can be applied during writes even when Rtt_Nom is desabled.
Dring write leveling, Dynamic ODT is not avaiable.
3. Optiona in DDR3 SDRAM: If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond
the specified address range will be lost if self-refresh is entered. Data integrity will be maintained if tREF conditions are
met and no self-refresh command is issued.
A1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
Full
Half
: Bank 0 to Bank 3
Quarter: Bank 0 and Bank 1
1/8
: Bank 0
3/4
: Bank 2 to Bank 7
Half
: Bank 4 to Bank 7
Quarter: Bank 6 and Bank 7
1/8
: Bank 7
A0
0
1
0
1
0
1
0
1
(BA [2:0]
= 000, 001, 010, 011)
(BA [2:0]
= 000, 001)
(BA [2:0]
= 000)
(BA [2:0]
= 010, 011, 100, 101,110 ,111)
(BA [2:0]
= 100, 101, 110, 111)
(BA [2:0]
= 110, 111)
(BA [2:0]
= 111)
Partial array self-refresh
Refresh array
A7
0
Self-refresh range
Normal self-refresh
Extend temperature
self-refresh
A6
0
1
Auto self-refresh method
Manual SR reference
(SRT)
ASR enable
(Optional)
A5
0
0
0
0
1
1
1
1
A4
0
0
1
1
0
0
1
1
A3
0
1
0
1
0
1
0
1
CAS write Latency (CWL)
5 (tCK
≥ 2.5ns)
6 (2.5ns > tCK
≥ 1.875ns)
7 (1.875ns > tCK
≥ 1.5ns)
8 (1.5ns > tCK
≥ 1.25ns)
Reserved
Reserved
Reserved
Reserved
A9
0
1
0
1
A10
0
0
1
1
Rtt_WR
Dynamic ODT off (write does not
affect Rtt value)
RZQ/4
RZQ/2
Reserved
1
A14
MR2 Programming



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