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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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EDJ2104BASE bảng dữ liệu(PDF) 57 Page - Elpida Memory |
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EDJ2104BASE bảng dữ liệu(HTML) 57 Page - Elpida Memory |
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57 / 148 page  EDJ2104BASE, EDJ2108BASE Preliminary Data Sheet E1505E20 (Ver. 2.0) 57 -AE -8C Data rate (Mbps) 1066 800 Parameter Symbol min. max. min. max. Unit Notes DQS falling edge setup time to rising CK tDSS 0.2 0.2 tCK (avg) 24, 36 DQS input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK (avg) 34, 35 DQS input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK (avg) 33, 35 DQS output high time tQSH 0.38 0.38 tCK (avg) 12, 13, 38 DQS output low time tQSL 0.38 0.38 tCK (avg) 12, 13, 38 Mode register set command cycle time tMRD 4 4 nCK Mode register set command update delay tMOD 15 15 ns 27 tMOD 12 12 nCK 27 Read preamble tRPRE 0.9 0.9 tCK (avg) 1, 19, 38 Read postamble tRPST 0.3 0.3 tCK (avg) 11, 12, 13, 38 Write preamble tWPRE 0.9 0.9 tCK (avg) 1 Write postamble tWPST 0.3 0.3 tCK (avg) 1 Write recovery time tWR 15 15 ns 26 Auto precharge write recovery + precharge time tDAL WR + RU (tRP/tCK (avg)) WR + RU (tRP/tCK (avg)) nCK Multi-Purpose register recovery time tMPRR 1 1 nCK 29 Read to write command delay (BC4MRS, BC4OTF) tRTW RL + tCCD/2 + 2nCK − WL RL + tCCD/2 + 2nCK − WL (BL8MRS, BL8OTF) tRTW RL + tCCD + 2nCK − WL RL + tCCD + 2nCK − WL Internal write to read command delay tWTR 7.5 7.5 ns 18, 26, 27 tWTR 4 4 nCK 18, 26, 27 Internal read to precharge command delay tRTP 7.5 7.5 ns 26, 27 tRTP 4 4 nCK 26, 27 Active to READ with auto precharge command delay tRAP tRCD min tRCD min 28 Minimum CKE low width for self- refresh entry to exit timing tCKESR tCKE (min.) +1nCK tCKE (min.) +1nCK Valid clock requirement after self- refresh entry or power-down entry tCKSRE 10 10 ns 27 tCKSRE 5 5 nCK 27 Valid clock requirement before self-refresh exit or power-down exit tCKSRX 10 10 ns 27 tCKSRX 5 5 nCK 27 |
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