TMP320LC2401AVFS datasheet(68/88 Pages) TI

68 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

low-power mode timing

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]

(see Figure 30, Figure 31, and Figure 32)

PARAMETER

LOW-POWER MODES

MIN

TYP

MAX

UNIT

td(WAKE-A)

Delay time, CLKOUT switching to

IDLE1

LPM0

× tc(CO)

td(WAKE-A)

Delay time, CLKOUT switching to

program execution resume

IDLE2

LPM1

× tc(CO)

td(IDLE-COH)

Delay time, Idle instruction executed to

CLKOUT high

IDLE2

LPM1

4tc(CO)

td(WAKE-OSC)

Delay time, wake-up interrupt

asserted to oscillator running

HALT

{PLL/OSC power down}

LPM2

OSC start-up

and PLL lock

time

td(IDLE-OSC)

Delay time, Idle instruction executed to

oscillator power off

{PLL/OSC power down}

LPM2

4tc(CO)

td(EX)

Delay time, reset vector executed after RS high

36H

WAKE INT§

CLKOUT†‡

A0−A15

td(WAKE−A)

† In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.

‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform

depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the

XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

§ WAKE INT can be any valid interrupt or RESET.

Figure 30. IDLE1 Entry and Exit Timing − LPM0

td(WAKE−A)

td(IDLE−COH)

WAKE INT§

CLKOUT†‡

A0−A15

† In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.

‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform

depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the

XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

§ WAKE INT can be any valid interrupt or RESET.

Figure 31. IDLE2 Entry and Exit Timing − LPM1

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