TMP320LC2401AVFS datasheet(40/88 Pages) TI

40 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PWM characteristics

Characteristics of the PWMs are as follows:

D 16-bit registers

D Programmable deadband for the PWM output pairs, from 0 to 12 µs

D Minimum deadband width of 25 ns

D Change of the PWM carrier frequency for PWM frequency wobbling as needed

D Change of the PWM pulse widths within and after each PWM period as needed

D External-maskable power and drive-protection interrupts

D Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space

vector PWM waveforms

D Minimized CPU overhead using auto-reload of the compare and period registers

D The PWM pins are driven to a high-impedance state when the PDPINTA pin is driven low and after

PDPINTA signal qualification. The status of the PDPINTA pin (after qualification) is reflected in bit 8 of the

COMCONA register.

capture unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP

timer counter is captured and stored in the two-level-deep FIFO stack when selected transitions are detected

on the capture input pin, CAP1. The capture unit consists of three capture circuits.

The capture unit includes the following features:

D One 16-bit capture control register, CAPCONA (R/W)

D One 16-bit capture FIFO status register, CAPFIFOA

D Selection of GP timer 1/2 as the time base

D One 16-bit 2-level-deep FIFO stack

D One capture input pin (CAP1). [The input is synchronized with the device (CPU) clock. In order for a

transition to be captured, the input must hold at its current level to meet two rising edges of the device clock.]

D User-specified transition (rising edge, falling edge, or both edges) detection

D One maskable interrupt flag

input qualifier circuitry

An input-qualifier circuitry qualifies the input signal to the CAP1, XINT1/2, ADCSOC, and PDPINTA pins in the

2401A device. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal

input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller

than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low

for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether

6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches.

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