TMP320LC2401AVFS datasheet(62/88 Pages) TI

62 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

VLOAD

IOL

IOH

Output

Under

Test

Ω

Where:

IOH

−2 mA (all outputs)

VLOAD =

1.5 V

50-pF typical load-circuit capacitance

Figure 23. Test Load Circuit

signal transition levels

The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference

voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high

level of 2.4 V and to a maximum logic-low level of 0.4 V.

Figure 24 shows output levels.

0.4 V (VOL)

20%

2.4 V (VOH)

80%

Figure 24. Output Levels

Output transition times are specified as follows:

D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the

total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage

range and lower.

D For alow-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage

range and higher and the level at which the output is said to be high is 80% of the total voltage range and

higher.

Figure 25 shows the input levels.

0.8 V (VIL)

10%

2.0 V (VIH)

90%

Figure 25. Input Levels

Input transition times are specified as follows:

D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%

of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage

range and lower.

D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%

of the total voltage range and higher and the level at which the input is said to be high is 90% of the total

voltage range and higher.

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