EPCS4 datasheet(28/38 Pages) ALTERA

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3–28

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

Timing Information

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

Figure 3–19 shows the timing waveform for the serial configuration device's read

operation.

Table 3–17 defines the serial configuration device timing parameters for read

operation.

1 Existing batches of EPCS1 and EPCS4 manufactured on 0.15 µm process geometry

support AS configuration up to 40 MHz. However, batches of EPCS1 and EPCS4

manufactured on 0.18 µm process geometry support only up to 20 MHz. EPCS16,

EPCS64, and EPCS128 are not affected.

f For information about product traceability and transition date to differentiate

between 0.15 µm process geometry and 0.18 µm process geometry EPCS1 and EPCS4,

refer tothe Process Change Notification PCN 0514: Manufacturing Changes on EPCS

Family.

Figure 3–19. Read Operation Timing

nCS

DCLK

DATA

ASDI

tnCLK2D

tCL

tCH

tODIS

Bit N

Bit 0

Bit N

1

Add_Bit 0

Table 3–17. Read Operation Parameters

Symbol

Parameter

Min

Max

Unit

fRCLK

Read clock frequency (from FPGA or

embedded processor) for read bytes

operation

—20

MHz

tCH

DCLK

high time

—

tCL

DCLK

low time

—

tODIS

Output disable time after read

—

tnCLK2D

Clock falling edge to data

—

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