EPCS4 datasheet(27/38 Pages) ALTERA

27 / 38 page

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

3–27

Timing Information

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Timing Information

Figure 3–18 shows the timing waveform for write operation to the serial configuration

device.

Table 3–16 defines the serial configuration device timing parameters for write

operation.

Figure 3–18. Write Operation Timing

nCS

DCLK

ASDI

DATA

tNCSH

tDSU

tNCSSU

tCH

tCL

tCSH

tDH

Bit n

Bit 0

Bit n

1

High Impedance

Table 3–16. Write Operation Parameters

Symbol

Parameter

Min

Typ

Max

Unit

fWCLK

Write clock frequency (from FPGA, download cable, or

embedded processor) for write enable, write disable,

read status, read silicon ID, write bytes, erase bulk, and

erase sector operations

——25

MHz

tCH

DCLK

high time

—

tCL

DCLK

low time

—

tNCSSU

Chip select (nCS) setup time

—

tNCSH

Chip select (nCS) hold time

—

tDSU

Data (ASDI) in setup time before rising edge on DCLK

5—

—

tDH

Data (ASDI) hold time after rising edge on DCLK

5—

—

tCSH

Chip select high time

100

—

tWB (1)

Write bytes cycle time for EPCS1, EPCS4, EPCS16, and

EPCS64

—1.5

Write bytes cycle time for EPCS128

—

2.5

tWS (1)

Write status cycle time

—

tEB (1)

Erase bulk cycle time for EPCS1

—

Erase bulk cycle time for EPCS4

—

Erase bulk cycle time for EPCS16

—

Erase bulk cycle time for EPCS64

—

160

Erase bulk cycle time for EPCS128

—

105

250

tES (1)

Erase sector cycle time for EPCS1, EPCS4, EPCS16,

and EPCS64

—2

Erase sector cycle time for EPCS128

—

Note to Table 3–16:

(1) These parameters are not shown in Figure 3–18.

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