EPCS4 datasheet(19/38 Pages) ALTERA

19 / 38 page

Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

3–19

Serial Configuration Device Memory Access

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Write Status Operation

The write status operation code is b'0000 0001, with the MSB listed first. Use the

write status operation to set the status register block protection bits. The write status

operation has no effect on the other bits. Therefore, you can implement this operation

to protect certain memory sectors, as defined in Table 3–9 through Table 3–13. After

setting the block protect bits, the protected memory sectors are treated as read-only

memory. You must execute the write enable operation before the write status

operation so the device sets the status register’s write enable latch bit to 1.

The write status operation is implemented by driving nCS low, followed by shifting in

the write status operation code and one data byte for the status register on the ASDI

pin. Figure 3–10 shows the timing diagram for the write status operation. nCS must be

driven high after the eighth bit of the data byte has been latched in, otherwise, the

write status operation is not executed.

Immediately after nCS drives high, the device initiates the self-timed write status

cycle. The self-timed write status cycle usually takes 5 ms for all serial configuration

devices and is guaranteed to be less than 15 ms (refer to tWS in Table 3–16). You must

account for this delay to ensure that the status register is written with desired block

protect bits. Alternatively, you can check the write in progress bit in the status register

by executing the read status operation while the self-timed write status cycle is in

progress. The write in progress bit is 1 during the self-timed write status cycle, and 0

when it is complete.

Figure 3–9. Read Status Operation Timing Diagram

nCS

DCLK

ASDI

DATA

101112131415

765432107

2107

6543

Operation Code

MSB

Status Register Out

High Impedance

Figure 3–10. Write Status Operation Timing Diagram

nCS

DCLK

ASDI

DATA

101112131415

Operation Code

Status Register

76543210

MSB

High Impedance

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