TLK6002 datasheet(26/96 Pages) TI

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LOSA

6.11 (Ch A)

GPI1

6.9 (Ch A)

Channel A InSync

6.8 (Ch A)

PLL Locked (Ch A)

6.3 (Ch A)

8b/10bInvalidCode (Ch A)

10.14 (Ch A)

ARSLocked (Ch A)

6.10 (Ch A)

LossofSignal (Ch A)

7.7 (Ch A)

AGCLOCK (Ch A)

7.6 (Ch A)

AZDONE (Ch A)

TLK6002

SLLSE34 – MAY 2010

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4. Receive 8b/10b Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR'd with

LOS condition(s) when enabled – (Register 6.3 enabled). The occurrence of an 8b/10b decode error

(invalid code word or disparity error) is optionally OR'd (disabled by default) with the other internally

generated loss of signal conditions (per channel).

5. ARS_Locked (ARS State Machine Currently Locked) – Inverted and Logically OR'd with LOS

condition(s) when enabled – (Register 10.14 enabled). ARS State Machine unlocked indication is

optionally OR'd (disabled by default) with the other internally generated loss of signal conditions (per

channel).

6. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR'd with LOS

conditions(s) when enabled – (Register 7.7 enabled). RX SERDES adaptive gain control unlocked

indication is optionally OR'd (disabled by default) with the other internally generated loss of signal

conditions (per channel).

7. AZDONE (Auto Zero Calibration Done) – Inverted and Logically OR'd with LOS conditions(s) when

enabled – (Register 7.6 enabled). RX SERDES auto zero not done indication is optionally OR'd

(disabled by default) with the other internally generated loss of signal conditions (per channel).

See Figure 2-8, which shows the detailed implementation of the LOSA signal.

NOTE: LOSA is asserted (driven high) during a failing condition, and deasserted (driven low) otherwise. Any combinations of

status signals may be enabled onto LOSA/B based on MDIO register bits indicated above. LOSB circuit is similar.

Figure 2-8. LOSA – Logic Circuit Implementation

Description

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