TLK6002 datasheet(34/96 Pages) TI

34 / 96 page

TLK6002

SLLSE34 – MAY 2010

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that greater than 4.5 seconds of time can be programmed per attempted interval. Thus, the ARS state

machine will attempt to determine a particular serial rate for a programmable number of reference clock

periods where channel synchronization cannot be established before attempting the next (and different)

lower serial bit rate, in a repeating/looping fashion when the lowest enabled serial bit rate is attempted

unsuccessfully.

The ARS function overrides the following SERDES register settings (RATE_TX / RATE_RX / PLL_MULT).

MDIO writes to these registers do not impact the actual values controlling internal SERDES device

settings as long as ARS is enabled for that channel, and reads instead return the current settings (which

may or may not be valid) as controlled by the ARS state machine (and does so until ARS is disabled).

Table 2-7. ARS Looped Device Settings (Looping order highest

→ lowest enabled bit rate)

Reference Clock (MHz)

ARS Rate / Scale / Multiplier Settings Per Reference Clock

153.6

122.88

307.2

Standard

Serial Rate (Gbps)

Rate

Rate Scale

SERDES Multiplier Setting Loop

CPRI

0.6144

Eighth

OBSAI

0.768

Eighth

CPRI

1.2288

Quarter

OBSAI

1.536

Quarter

CPRI

2.4576

Half

CPRI/OBSAI

3.072

Half

CPRI

4.9152

Full

0.5

CPRI/OBSAI

6.144

Full

0.5

Description

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