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TLK6002 bảng dữ liệu(PDF) 40 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver
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TLK6002 bảng dữ liệu(HTML) 40 Page - Texas Instruments

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TLK6002
SLLSE34 – MAY 2010
www.ti.com
2.23 Output Clock Selection (CLK_OUT_P/N)
Table 2-9 details CLK_OUT_P/N as a function of device settings.
Table 2-9. CLK_OUT_P/N Frequencies (ARS Enabled and Disabled)
Selected Channel A
Selected Channel B
RATE_A[2:0]
RATE_B[2:0]
CLK_OUT_SEL
CLK_OUT_P/N
REFCLK Frequency (MHz)
REFCLK Frequency (MHz)
Indicated By ARS_REF_FREQ
Indicated By ARS_REF_FREQ
000/001/010/011
000/001/010/011
0
RXBCLK_A/(0.5:4)
x
x
000/001/010/011
000/001/010/011
1
RXBCLK_B/(0.5:4)
x
x
110
Not 110
x
153.6 MHz (ppm 0 to RXAP/N)
153.6
x
110
Not 110
x
61.44 MHz (ppm 0 to RXAP/N)
122.88
x
110
Not 110
x
153.6 MHz (ppm 0 to RXAP/N)
307.2
x
110
Not 110
x
61.44 MHz (ppm 0 to RXAP/N)
245.76
x
Not 110
110
x
153.6 MHz (ppm 0 to RXBP/N)
x
153.6
Not 110
110
x
61.44 MHz (ppm 0 to RXBP/N)
x
122.88
Not 110
110
x
153.6 MHz (ppm 0 to RXBP/N)
x
307.2
Not 110
110
x
61.44 MHz (ppm 0 to RXBP/N)
x
245.76
101
000/001/010/011
0
153.6 MHz (ppm 0 to RXAP/N)
153.6
x
101
000/001/010/011
0
61.44 MHz (ppm 0 to RXAP/N)
122.88
x
101
000/001/010/011
0
153.6 MHz (ppm 0 to RXAP/N)
307.2
x
101
000/001/010/011
0
61.44 MHz (ppm 0 to RXAP/N)
245.76
x
101
000/001/010/011
1
RXBCLK_B/(0.5:4)
x
x
000/001/010/011
101
1
153.6 MHz (ppm 0 to RXBP/N)
x
153.6
000/001/010/011
101
1
61.44 MHz (ppm 0 to RXBP/N)
x
122.88
000/001/010/011
101
1
153.6 MHz (ppm 0 to RXBP/N)
x
307.2
000/001/010/011
101
1
61.44 MHz (ppm 0 to RXBP/N)
x
245.76
000/001/010/011
101
0
RXBCLK_A/(0.5:4)
x
x
101
101
0
153.6 MHz (ppm 0 to RXAP/N)
153.6
x
101
101
0
61.44 MHz (ppm 0 to RXAP/N)
122.88
x
101
101
0
153.6 MHz (ppm 0 to RXAP/N)
307.2
x
101
101
0
61.44 MHz (ppm 0 to RXAP/N)
245.76
x
101
101
1
153.6 MHz (ppm 0 to RXBP/N)
x
153.6
101
101
1
61.44 MHz (ppm 0 to RXBP/N)
x
122.88
101
101
1
153.6 MHz (ppm 0 to RXBP/N)
x
307.2
101
101
1
61.44 MHz (ppm 0 to RXBP/N)
x
245.76
111
101/110
x
153.6 MHz (ppm 0 to RXBP/N)
x
153.6
111
101/110
x
61.44 MHz (ppm 0 to RXBP/N)
x
122.88
111
101/110
x
153.6 MHz (ppm 0 to RXBP/N)
x
307.2
111
101/110
x
61.44 MHz (ppm 0 to RXBP/N)
x
245.76
111
000/001/010/011/111
0
RXBCLK_A/(0.5:4)
x
x
111
000/001/010/011/111
1
RXBCLK_B/(0.5:4)
x
x
101/110
111
x
153.6 MHz (ppm 0 to RXAP/N)
153.6
x
101/110
111
x
61.44 MHz (ppm 0 to RXAP/N)
122.88
x
101/110
111
x
153.6 MHz (ppm 0 to RXAP/N)
307.2
x
101/110
111
x
61.44 MHz (ppm 0 to RXAP/N)
245.76
x
000/001/010/011/111
111
0
RXBCLK_A/(0.5:4)
x
x
000/001/010/011/111
111
1
RXBCLK_B/(0.5:4)
x
x
2.24 MDIO Management Interface
The TLK6002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK6002 is possible without use of this interface. However, some
features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The port address is determined by control pins (see Table 2-10).
40
Description
Copyright © 2010, Texas Instruments Incorporated
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