TLK6002 datasheet(70/96 Pages) TI

70 / 96 page

TOL

RXCLK_x

RDx

tPERIOD

tSETUP

tHOLD tSETUP

tHOLD

VOH(ac)

VDDQ/2

VOL(ac)

VDDQ/2

VOL(ac)

VOH(ac)

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Input Jitter Definition

NOTE: JTOL = JR + JDR, where JTOL is the receive jitter tolerance, JDR is the received deterministic jitter, and JR is the

Gaussian random edge jitter distribution at a maximum BER = 10-12 for CPRI link and BER = 10-15 for OBSAI (RP3)

link.

4.10

HSTL Output Switching Characteristics (DDR Timing Mode Only)

(over recommended operating conditions unless otherwise noted).

PARAMETER

CONDITION

MIN

MAX

UNIT

tsetup

RDx(1) setup prior to RXCLK_x transition high or

Source Centered. See Figure 4-12(2)

0.15 ×

low

tperiod

thold

RDx hold after RXCLK_x transition high or low

Source Centered. See Figure 4-12(2)

0.15 ×

tperiod

Tduty

RXCLK_x(3) Duty Cycle

Source Centered and Source Aligned.(2)

45%

55%

tperiod

RXCLK_x Period

Source Centered and Source Aligned.

6.4

85.11

Tfreq

RXCLK_x Frequency

Source Centered and Source Aligned.

11.75

156.25

MHz

Tpd

RXCLK_x rising or falling to RDx valid.

Source Aligned See Figure 4-13(2)

–0.10 ×

+0.10 ×

tperiod

(1)

RDx refers to either RDA or RDB for channels A and B respectively

(2)

Cload = 10pF, using timing reference of (VDDQA/B)/2.

(3)

RXCLK_x refers to RXCLK_A or RXCLK_B for channels A and B respectively.

Figure 4-12. HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements

ELECTRICAL SPECIFICATIONS

Submit Documentation Feedback

Product Folder Link(s): TLK6002

TLK6002 bảng dữ liệu(PDF) 70 Page - Texas Instruments

TLK6002 bảng dữ liệu(HTML) 70 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

bảng dữ liệu tải về

Link URL