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TLK6002 bảng dữ liệu(PDF) 22 Page - Texas Instruments

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tên linh kiện TLK6002
Giải thích chi tiết về linh kiện  Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver
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TLK6002 bảng dữ liệu(HTML) 22 Page - Texas Instruments

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RXCLK_A
RDA_ [19:0 ]
Data
Data
Data
Data
Data
SourceCentered (DDR)
Source Aligned (DDR)
Data
Data
Data
Data
FallingEdge Aligned (RisingEdgeSampled)(SDR)
RisingEdge Aligned (FallingEdgeSampled )(SDR)
RDA_ [19:0]
RDA_ [19:0]
RDA_ [19:0]
tSETUP
tHOLD
tSETUP
tHOLD
TLK6002
SLLSE34 – MAY 2010
www.ti.com
2.7
16-bit DDR (Double Data Rate) Mode (8b/10b Encoder/Decoder Enabled)
When DDR is enabled with the 8b/10b encoder enabled, the data format is identical to that of "16-bit SDR
(Single Data Rate) Mode (8b/10b Encoder/Decoder Enabled)" mode, except that four symbols are
transferred per parallel interface clock cycle instead of two. See the referenced previous section for further
details.
2.8
Parallel Interface Clocking Modes
The TLK6002 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. TLK6002 also supports rising edge aligned and falling edge aligned SDR timing on the parallel
receive output bus. See Figure 2-4 for more details.
Figure 2-4. Receive Interface Timing – Source Centered/Aligned (Channel A is shown).
The transmit input timing modes are shown in Figure 2-5.
Transmit SDR/DDR input timing modes supported are similar to RX modes.
22
Description
Copyright © 2010, Texas Instruments Incorporated
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