MAC7200 datasheet(158/976 Pages) FREESCALE

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Exception Handling

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

fixed address. For purposes of explanation in this document, that address will be assumed to be

$0000_0000.

7.2.1

Reset

Address: $0000 0000

As discussed in Chapter 9, “Device Memory Map”, the physical memory or bus to which this address is

mapped can be re-located both in hardware and in software.

7.2.2

Undefined Instruction

Address: $0000 0004

There are no additional co-processors in the system.

7.2.3

Software Interrupt

Address: $0000 0008

There is no special functionality on the MAC72xx to support SWIs.

7.2.4

Prefetch (Instruction) Abort

Address: $0000 000C

A special set of registers has been added to the MCM to support easier debugging of both Instruction and

Data Aborts. These “core fault” registers will store the last address and transfer modifiers (size, type, etc.)

that caused an Instruction or Data Abort (i.e.-the last address that caused a Transfer Error on the ARM7

native bus). The associated read/write data will not be stored.

On the MAC72xx, there are several sources of aborts that can be generated throughout the bus hierarchy,

including the following:

•

AXBS

— Access to an unavailable slave port on the AXBS (S2, S4 and S6 on the MAC72xx). See

Section 15.7.2, “Master/Slave Interface” for more details.

— Writing to an AXBS slave address when the RO bit in the slave’s SGPCR register is set. See

Section 15.7.2, “Master/Slave Interface” for more details.

•

FlexBus

— Access to the FlexBus hits no chip-select address ranges

•Flash

— Access to Flash blocked by the WACC/SACC/DACC access protection in the Flash Controller

and MCM

— Flash access produces an ECC error

— Flash access produces a Read-while-Write error

•SRAM

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