MAC7200 datasheet(157/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

Chapter 7

Exceptions

7.1

Introduction

The ARM7 core on the MAC72xx supports the following exceptions:

The ARM7 core does not support a relocatable exception table. Therefore, relocation of exception vectors

is done by relocating the base address of a particular system resource. This is done primarily through the

programming of the AXBS.

7.2

Exception Handling

This section lists any special features that have been added to the MAC72xx to better support the standard

ARM7 exceptions. It does not list the features of the Interrupt Controller, except where those features have

an impact on exception handling in the system.

Besides the requirements below for each exception type, there is a general requirement that the entire

exception table be relocated. This requirement comes from the Primary Boot Loader concept described in

Section 9.18, “System Boot Sequence”. In summary, the exception table must be relocatable into a

non-FLASH, writable space during the boot process. One way to implement this is to implement an

interrupt controller that returns an address for each exception. However, the MAC72xx interrupt controller

only returns a vector number (or index), which can be used as an address offset/multiplier. This scheme is

of limited use in the Primary/Secondary Boot Loader, where the final exception vector address should be

programmable by the Secondary Boot Loader. Another alternative is to provide relocation of the exception

table via a software configurable bit in the core itself (like the ColdFire architecture). However, the

ARM7TDMI-S does not support this. The final alternative is to fix the exception table at a particular

address (both in the core and in the Primary Boot Loader), and then to re-map particular memories to this

Table 7-1. ARM Exception Table

Vector

Address

Exception

Mode on entry

I State

on entry

F State

on entry

Priority

(1=highest)

$0000 0000

Reset

Supervisor

Disabled

$0000 0004

Undefined Instruction

Undefined

$0000 0008

Software Interrupt (SWI)

Supervisor

Disabled

$0000 000C

Abort (Prefetch)

Abort

$0000 0010

Abort (Data)

Abort

$0000 0018

Reserved

$0000 0018

IRQ

Disabled

$0000 001C

FIQ

FIRQ

Disabled

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