MAC7200 datasheet(141/976 Pages) FREESCALE

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Clock Generation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

Figure 5-3. Timing of CRG Generated Clocks

5.2.1

Clock Source Selection

With two oscillator modes, and the ability to bypass the PLL, there are four main clock selection modes

that the system may be run in:

•

Automatic Level Control (ALC) 1:1 Mode - In this mode, the oscillator is enabled, and the PLL is

bypassed.

•

Automatic Level Control (ALC) PLL Mode - In this mode, the oscillator is enabled, and the PLL

is enabled.

•

External Clock 1:1 Mode - In this mode, the oscillator is bypassed, and the PLL is bypassed.

•

External Clock PLL Mode - In this mode, the oscillator is bypassed, and the PLL is enabled.

For information on selecting the oscillator mode, please refer to Section 24.8.1, “OSC Mode Selection”.

The enabling or bypassing of the PLL is done with the PLLSEL bit in the CLKSEL register in the CRG

module.

The oscillator mode is chosen by a combination of the JTAG SC4 register and the XCLKS hardware

configuration pin, as follows:

Note that the PLL always comes up disabled (PLLSEL = 0) after a System or Power On Reset, and must

be explicitly enabled by the boot software.

In addition to the above modes, the FlexCAN, SWT and RTI all have some level of configurability with

respect to clock source.

Table 5-2. Clock Source Selection

XCLKS

PLLSEL

Mode

ALC 1:1 Mode

ALC PLL Mode

External Clock 1:1 Mode

External Clock PLL Mode

System Clock

Peripheral Bus Clock

2 3 4 1 234 1 2 34 1 2 3 41 23 4 12341

RTI Clock

SWT Clock

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