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MAC7200 bảng dữ liệu(PDF) 304 Page - Freescale Semiconductor, Inc |
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MAC7200 bảng dữ liệu(HTML) 304 Page - Freescale Semiconductor, Inc |
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304 / 976 page  The SPP DMA Controller Module (SPP_DMA2) MAC7200 Microcontroller Family Reference Manual, Rev. 2 226 Freescale Semiconductor Figure 12-19 and Table 12-23 define word 2 of the TCDn structure, the nbytes field. Figure 12-20 and Table 12-24 define word 3 of the TCDn structure, the slast field. Register address: DMA_Offset + 0x1000 + (32 x n) + 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R nbytes[31:16] W Reset ———————————————— 15 14 13 12 11 10 9876543210 R nbytes[15:00] W Reset ———————————————— = Unimplemented Figure 12-19. TCDn Word 2 (TCDn.nbytes) Field Table 12-23. TCDn Word 2 (TCDn.nbytes) Field Description Field Description 31–0 nbytes[31:0] Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into the dma_engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible operation and cannot be stalled or halted. Once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. If the major iteration count is completed, additional processing is performed. The nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4GB transfer. |
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