MAC7200 datasheet(302/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

224

Freescale Semiconductor

Figure 12-17 and Table 12-21 define word 0 of the TCDn structure, the saddr field.

Figure 12-18 and Table 12-22 define word 1 of the TCDn structure, the soff and transfer attribute fields.

0x1000 + (32 x n) + 0x04

Transfer Attributes

(smod, ssize, dmod, dsize)

Signed Source Address Offset (soff)

0x1000 + (32 x n) + 0x08

Inner “Minor” Byte Count (nbytes)

0x1000 + (32 x n) + 0x0c

Last Source Address Adjustment (slast)

0x1000 + (32 x n) + 0x10

Destination Address (daddr)

0x1000 + (32 x n) + 0x14

Current “Major” Iteration Count (citer)

Signed Destination Address Offset (doff)

0x1000 + (32 x n) + 0x18

Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)

0x1000 + (32 x n) + 0x1c

Beginning “Major” Iteration Count (biter)

Channel Control/Status

(bwc, major.linkch, done, active, major.e_link,

e_sg, d_req, int_half, int_maj, start)

saddr[31:16]

Reset

————————————————

9876543210

saddr[15:00]

Reset

————————————————

= Unimplemented

Figure 12-17. TCDn Word 0 (TCDn.saddr) Field

Table 12-21. TCDn Word 0 (TCDn.saddr) Field Description

Field

Description

31–0

saddr[31:0]

Source address. Memory address pointing to the source data.

Table 12-20. TCDn 32-bit Memory Structure

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