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MAC7200 bảng dữ liệu(PDF) 277 Page - Freescale Semiconductor, Inc

tên linh kiện MAC7200
Giải thích chi tiết về linh kiện  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MAC7200 bảng dữ liệu(HTML) 277 Page - Freescale Semiconductor, Inc

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Overview of the MAC7200 Implementation
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
199
— Initiation via a channel-to-channel linking mechanism for continuous transfers. This method
allows a channel to be started once another channel has completed.
— Peripheral-paced hardware requests. The method allows the channel activation to be controlled
by the peripheral itself.
Note than in all three methods, one activation per execution of the minor loop is required.
If explicit software activation is chosen for a channel, perform the following series of steps:
1. Configure the channel’s TCD with the correct source and destination information.
2. Write the ‘start’ bit in Word 7 of the channel’s TCD to activate the channel and start transfers.
If channel-to-channel linking is chosen for a channel, perform the following series of steps:
1. Configure the channel’s TCD with the correct source and destination information, ensuring that the
‘start’ bit in Word 7 is cleared.
2. Set the ‘e_link’ bit in Word 7 of the channel’s TCD.
3. Program the ‘linkch[5:0]’ bits in Word 7 of the channel’s TCD.
If peripheral paced hardware activation is chosen for a channel, perform the following series of steps:
1. Ensure that the DMA channel you want to use is disabled by clearing the corresponding bit in the
DMAERL register.
2. Configure the channel’s TCD with the correct source and destination information, ensuring that the
‘start’ bit in Word 7 is cleared.
3. Configure the DMA Channel Mux. For basic operation (no triggering), you can write the
CONFIGn register in the DMA Channel Mux with $80 | <Channel Source>.
4. Set the corresponding DMAERL register bit. If the ’d_req’ bit in the TCD is set, then the bit in the
DMAERL register will be automatically cleared after completion of the major loop. This
guarantees that the channel will not be re-activated after completion without explicit software
intervention.
5. Configure the peripheral to enable DMA transfers. Please refer to the documentation for the
particular peripheral for more details.
12.1.6.4
Using the DMA
Accessing multiple registers
Use the scatter-gather feature of the eDMA to construct more complex sets of transactions in order to (for
example) access peripherals with separate control and data transmit/receive registers. Assuming channel
1 is used, the following sequence illustrates this:
1. Peripheral requests a DMA transfer (also applies to software and triggered requests)
2. TCD1a transfers data to the peripheral’s control register
3. TCD1a executes a scatter-gather operation, and reloads its TCD descriptor with TCD1b
4. TCD1b has the TCD.start bit already set in the descriptor
5. The transfer request is automatically issued once TCD1b is loaded
6. TCD1b transfers data to the peripheral’s data register (as many loops as required)



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