MAC7200 datasheet(276/976 Pages) FREESCALE

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Overview of the MAC7200 Implementation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

198

Freescale Semiconductor

12.1.6.3.3

DEBUG Mode Behavior

In any real-time system, the debugging of code affected by real-time external events can often be very

difficult. For this reason, flexibility in the ability to selectively enable/disable certain kinds of events when

the system is in DEBUG mode is provided. In the DMA, the user has the flexibility to configure the

execution of the major loop counter in the current active channel in DEBUG mode. If desired, the EDBG

bit in the DMACR register can be set in order to stop the operation of a channel.

12.1.6.3.4

Transfer Control Descriptor (TCD)

Each channel has a corresponding TCD, which must be configured to specify the source and destination

information, as well as the minor and major loop counter information. Please refer to the DMA2 Block

Guide for detailed information on TCDs.

12.1.6.3.5

Channel Completion

The completion of a channel (i.e.-completion of the major loop counter) can be either interrupt driven or

polling driven, similar to the error signalling. If interrupt driven channel completion is desired, follow

these steps:

1. Enable interrupt on major loop counter completion by setting the ‘int_maj’ bit in Word 7 of the

channel’s TCD.

2. Once the interrupt is received (Interrupt #1-#16), clear the interrupt by clearing the corresponding

bit in the DMAINTL register. Individual bits can be easily cleared by writing to the DMACINT

that it is unnecessary to read the DMAINTL register before clearing it, as each DMA Channel on

the MAC72xx has a dedicated interrupt. The exact channel that caused the interrupt can be

determined solely by the Interrupt Vector number in the Interrupt Controller.

3. Besides producing an interrupt at the completion of a channel, the DMA is also capable of causing

an interrupt when the major loop counter is half completed. This feature can be activated by setting

the ‘int_half’ bit in Word 7 of the channel’s TCD. Note that in this case it is impossible to determine

whether an interrupt is signalling the completion of a channel or only the halfway completion of a

channel. The Interrupt Service Routine (ISR) that handles DMA channel interrupts must explicitly

keep track of this by itself.

To implement polling driven channel completion, following these steps:

1. Disable interrupt on major loop counter completion by clearing the ‘int_maj’ bit in Word 7 of the

channel’s TCD.

2. Determine the completion of a channel by continuously reading Word 7 of the channel’s TCD.

When the ‘done’ bit is set, the channel has completed.

12.1.6.3.6

Channel Activation Method

Each DMA Channel may be configured to use one of three channel activation methods available:

— Explicit software activation. This method allows the channel to be started explicitly by the

software at any time.

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