MAC7200 datasheet(265/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

187

11.11.5.3.3

Single Read Access

1. Initialize the Read/Write Access Address Register (RWA) through the JTAG access method

outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the Nexus

— Read Address

→ 32'hxxxxxxxx (read address)

2. Initialize the Read/Write Access Control/Status Register (RWCS) through the JTAG access

method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the

Nexus Register Index of 0x7 (see Table 11-21). Configure the bits as follows:

— Access Control (AC)

→ 1'b1 (to indicate start access)

—Map Select (MAP)

→ 3'b000 (primary memory map)

— Access Priority (PR)

→ 2'b00 (lowest priority)

— Read/Write (RW)

→ 1'b0 (read access)

— Word Size (SZ)

→ 3'b0xx (32-bit, 16-bit, 8-bit)

— Access Count (CNT)

→ 14'h0000 or 14'h0001(single access)

NOTE

Access Count (CNT) of 14'h0000 or 14'h0001 will perform a single access.

3. The Nexus block will then arbitrate for the AHB and the read data will be transferred from the AHB

to the RWD Register.

When the transfer completed without error (ERR=1'b0), the Nexus block asserts the RDY pin (see

Table 11-13 for detail on RDY) and sets the DV bit in the RWCS Register. This indicates that the

device is ready for the next access.

4. The data can then be read from the Read/Write Access Data Register (RWD) through the JTAG

access method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers

using the Nexus Register Index of 0xA (see Table 11-21).

NOTE

Only the RDY pin as well as the DV and ERR bits within the RWCS provide

Read/Write Access status to the external development tool. The

development tool needs to provide at least one clock after entering the

Run-Test-Idle state to ensure that the RDY pin is asserted

11.11.5.3.4

Block Read Access

1. For a block read access, follow Steps 1 and 2 outlined in Section 11.11.5.3.3, “Single Read

Access,” to initialize the registers, using a value greater than one (14'h0001) for the CNT field in

the RWCS Register.

2. The Nexus block will then arbitrate for the AHB and the read data will be transferred from the AHB

to the RWD Register.

When the transfer has completed without error (ERR=1'b0), the address from the RWA Register is

incremented to the next word size (specified in the SZ field) and the number from the CNT field is

decremented. The Nexus block will then assert the RDY pin. This indicates that the device is ready

for the next access.

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