MAC7200 datasheet(231/976 Pages) FREESCALE

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A7S Nexus3 Programmers Model

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

153

NOTE

System low power mode bits (LPS) functionality is determined at the

platform or SoC integration level. Any entry into a system-level low power

mode (LPS != 3'b000) will trigger a Debug Status Message sending the DS

related power-down modes. It is the tool’s responsibility to decode the

specific type of low power mode based on the encodings for the specific

SoC.

The CPU Low Power Mode bits (LPC) must be tied to the logic which

indicates that the ARM7 processor is in a powered-down state. The CPU

low power state may be independent of the SoC defined low power mode(s)

determined by the LPS bits.

11.10.3.4 User Base Address (UBA)

For ARM7 processors, Ownership Trace Messaging is implemented using the Nexus defined User Base

Address Register. The User Base Address Register defines the memory mapped base address for the

Offset see Table 11-21

Access: User read/write

DBG

LPS

LPC

000

Reset

000

876

321

000

Reset

000

Figure 11-7. Development Status Register (DS)

Table 11-24. DS Field Descriptions

Field

Description

DBG

ARM7 CPU Debug Mode Status

0 CPU not in Debug Mode

1 CPU in Debug Mode (DBGACK asserted)

30–28

LPS

ARM7 System Low Power Mode Status

000 Normal (Run) mode

nnn System Low Power Status (SoC level)

27–26

LPC

ARM7 CPU Low Power Mode Status

00 Normal (Run) mode

01 CPU in powered-down state

1x Reserved

25–0

Reserved for future functionality (read as 0)

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