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68HC05CL48 bảng dữ liệu(PDF) 116 Page - Motorola, Inc |
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68HC05CL48 bảng dữ liệu(HTML) 116 Page - Motorola, Inc |
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116 / 145 page ![]() GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA INSTRUCTION SET MC68HC05CL48 14-6 REV 2.0 and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 14-3 lists the jump and branch instructions. Table 14-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR |
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