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68HC05CL48 bảng dữ liệu(PDF) 49 Page - Motorola, Inc

tên linh kiện 68HC05CL48
Giải thích chi tiết về linh kiện  SPECIFICATION (General Release)
PDF  145 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

68HC05CL48 bảng dữ liệu(HTML) 49 Page - Motorola, Inc

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June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
INPUT/OUTPUT PORTS
MOTOROLA
REV 2.0
7-1
SECTION 7
INPUT/OUTPUT PORTS
In single-chip mode there are 24 pins arranged as 3 8-bit I/O port. The I/O ports
are programmable as either inputs or outputs under software control of the data
direction registers.
To avoid a glitch on the output pins, write data to the I/O Port Data Register before
writing a one to the corresponding Data Direction Register.
7.1
PARALLEL PORTS
Port A and B and C are 8-bit bidirectional port. Each Port pin is controlled by the
corresponding bits in a data direction register and a data register as shown in
Figure 7-1. The functions of the I/O pins are summarized in Table 7-1.
Figure 7-1. Port I/O Circuitry
Table 7-1. Port I/O Pin Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
Read/Write DDR
Write Data
Read Data
Data Direction
Register
Data
Register Bit
I/O
Pin
OUTPUT
Internal HC05
Data Bus
Reset
(RST)



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