68HC05CL48 datasheet(41/145 Pages) MOTOROLA

41 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

INTERRUPTS

MOTOROLA

REV 2.0

4-9

be enabled. This interrupt will vector to the interrupt service routine located at the

address speciﬁed by the contents of memory locations $FFF8 and $FFF9.

4.3.5 SPI Interrupt

The SPI interrupt is generated by serial peripheral interface as described in

Section 9. The interrupt enable bits for the SPI interrupt is in the SPI Control

the SPI interrupt to be enabled. These interrupts will vector to the same interrupt

service routine located at the address speciﬁed by the contents of memory

locations $FFF6 and $FFF7.

4.3.6 CTIMER, WTimer Interrupt (CORE TIMER, Watch Timer)

4.3.6.1

Core Timer Interrupt

The CTIMER interrupt is generated by the Core Timer when a core timer overﬂow,

or real time interrupt has occurred as described in Section 8. The interrupt enable

bits and ﬂags for the Core Timer interrupts are located in the Core Timer Control

and Status Register (CTCSR) located at $0008. The I-bit in the CCR must be

clear in order for the CTIMER interrupt to be enabled.

4.3.6.2

Watch Timer Interrupt

The WTimer interrupt is generated by the Watch Timer when a 1 second timer

overﬂow interrupt has occurred as described in Section 8. The interrupt enable

bits and ﬂags for the Watch Timer interrupt are located in the Watch Timer Control

and Status Register (WTCSR) located at $0023. The I-bit in the CCR must be

clear in order for the WTIMER interrupt to be enabled.

4.3.6.3

Interrupt Vector

The above two interrupts will vector to the same interrupt service routine located

at the address speciﬁed by the contents of memory locations $FFF0 and $FFF1.

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