68HC05CL48 datasheet(57/145 Pages) MOTOROLA

57 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-5

The divide-by-4 prescaler is also reset and the counter resumes normal counting

operation. All of the ﬂags and enable bits remain unaltered by this operation. If

access has previously been made to the high byte of the free running counter

($19 or $1B), then the reset counter operation terminates the access sequence.

Figure 8-3. Timer State Timing Diagram For Reset

8.1.2 Output Compare Registers

There are two output compare registers: output compare register 1 and output

compare register 2. Output compare registers can be used for several purposes

such as controlling an output waveform or indicating when a period of time has

elapsed. All bits are readable and writable and are not altered by the timer

hardware or reset. If the compare function is not needed, the two bytes of the

output compare register can be used as storage locations.

8.1.2.1

Output Compare Register 1

76543210

OC1H

$0015

READ

OC1:15

OC1:14

OC1:13

OC1:12

OC1:11

OC1:10

OC1:9

OC1:8

WRITE

RESET

UUUUUUUU

Internal Processor Clock

Internal Reset

Internal

Timer

Clocks

T00

T01

T10

T11

Counter (16bit)

RESET (External or POR)

$FFFC

$FFFD

$FFFE

$FFFF

NOTE: The Counter Register and Timer Control Register are the only ones affected by RESET.

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