68HC05CL48 datasheet(82/145 Pages) MOTOROLA

82 / 145 page

GENERAL RELEASE SPECIFICATION

June 6, 1997

MOTOROLA

ANALOG TO DIGITAL CONVERTER

MC68HC05CL48

10-2

REV 2.0

10.3

DIGITAL SECTION

10.3.1 Conversion Time

Each channel of conversion takes 32 clock cycles, which must be at a frequency

equal to or greater than 1 MHz.

10.3.2 Multi-Channel Operation

In User Mode a multiplexer allows the single A/D converter to select one of eight analog

signals, two of which are V

RH and VRL. The ATD3:0 are input signals to the multiplexer.

10.4

A/D STATUS AND CONTROL REGISTER (ADCSR)

The following paragraphs describe the function of the A/D Status and Control Register.

10.4.1 COCO - Conversions Complete

This read-only status bit is set when a conversion is completed, indicating that the A/D

Data Register contains valid results. This bit is cleared whenever the A/D Status and

Control Register is written and a new conversion automatically started, or whenever the

A/D Data Register is read. Once a conversion has been started by writing to the A/D

Status and Control Register, conversions of the selected channel will continue every 32

cycles until the A/D Status and Control Register is written again. In this continuous

conversion mode the A/D Data Register will be filled with new data, and the COCO bit set,

every 32 cycles. Data from the previous conversion will be overwritten regardless of the

state of the COCO bit prior to writing.

10.4.2 ADRC - A/D RC Oscillator Control

When the RC oscillator is selected (ADRC = 1) to be the A/D clock source, it requires a

time t

ADRC to stabilize. Results can be inaccurate during this time. If the CPU clock is

running below 1 Mhz, the RC oscillator must be used.

When ADRC =0, the A/D uses the CPU clock.

76543210

ADSCR

$0024

READ

COCO

ADRC

ADON

CH2

CH1

CH0

WRITE

RESET

UUUUUUUU

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