56F8014 datasheet(18/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 11

Freescale Semiconductor

2.2 56F8014 Signal Pins

After reset, each pin is configured for its primary function (listed first). Any alternate functionality must

be programmed.

Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

VDD_IO

Supply

I/O Power — This pin supplies 3.3V power to the chip I/O interface.

VSS_IO

Supply

VSS — These pins provide ground for chip logic and I/O drivers.

VSS_IO

VDDA

Supply

ADC Power — This pin supplies 3.3V power to the ADC modules. It

must be connected to a clean analog power supply.

VSSA

Supply

ADC Analog Ground — This pin supplies an analog ground to the

ADC modules.

VCAP

Supply

VCAP — Connect a 2.2 μF or greater bypass capacitor between this

pin and VSS_IO, which is required by the internal voltage regulator

for proper chip operation. See Section 10.2.1.

GPIOB6

(RXD)

(SDA1)

(CLKIN)

Input/

Output

Input

Input/

Output

Input

Input with

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Receive Data — SCI receive data input.

Serial Data — This pin serves as the I2C serial data line.

Clock Input — This pin serves as an optional external clock input.

After reset, the default state is GPIOB6. The alternative peripheral

functionality is controlled via the SIM (See Section 6.3.8) and the

CLKMODE bit of the OCCS Oscillator Control Register.

1. This signal is also brought out on the GPIOB1 pin.

Return to Table 2-2

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