56F8014 datasheet(69/124 Pages) FREESCALE

69 / 124 page

56F8014 Technical Data, Rev. 11

Freescale Semiconductor

6.3.5

Least Significant Half of JTAG ID (SIM_LSHID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads

$401D.

Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)

6.3.6

SIM Power Control Register (SIM_PWR)

This register controls the Standby mode of the large regulator. The large regulator derives the core digital

logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a

reduced-power Standby mode without interfering with part operation. Refer to the overview of

power-down modes and the overview of clock generation for more information on the use of large

regulator standby.

Figure 6-7 SIM Power Control Register (SIM_PWR)

6.3.6.1

Reserved—Bits 15–2

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.6.2

Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0

This bit controls the pull-up resistors on the IRQA pin.

•

00 = Large regulator is in Normal mode

•

01 = Large regulator is in Standby (reduced-power) mode

•

10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset

•

11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset

Note:

Standby mode can be used when the device operates below 200 kHz if the PLL is shut down.

6.3.7

CLKO Select Register (SIM_CLKOUT)

The CLKO select register can be used to multiplex out selected clocks generated inside the clock

generation and SIM modules. All functionality is for test purposes only and is subject to

unspecified latencies. Glitches may be produced when the clock is enabled or switched.

Base + $7

Read

Write

RESET

000

110

Base + $8

Read

LRSTDBY

Write

RESET

000

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