56F8014 datasheet(48/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 11

Freescale Semiconductor

5.5.1.1

LVI IPL—Bits 15–14

This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities

0 through 2 and is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.5.1.2

Reserved—Bits 13–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.5.1.3

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)— Bits 9–8

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.5.1.4

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)— Bits 7–6

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.5.1.5

EOnCE Trace Buffer Interrupt Priority Level

(TRBUF IPL)— Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

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