56F8014 datasheet(71/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 11

Freescale Semiconductor

•

01101 = Reserved for factory test—Continuous peripheral clock

•

01110 = Reserved for factory test—Continuous inverted peripheral clock

•

01111 = Reserved for factory test—Continuous high-speed peripheral clock

6.3.8

SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. To select

peripheral or GPIO control, program the corresponding bit in the GPIOx_PEREN register in the GPIO

module. (See MC56F8000RM, the 56F801x Peripheral Reference Manual, for details.) In some cases,

there are two possible peripherals as well as the GPIO functionality available for control of the I/O. In these

cases, the SIM_GPS register is used to determine which peripheral has control when the corresponding

I/O pin is configured in peripheral mode.

As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which

pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when

PEREN = 1.

Figure 6-9 Overall Control of Pads Using SIM_GPS Control

Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)

6.3.8.1

Quad Timer Clock Rate (TCR)—Bit 15

This bit selects the clock speed for the Quad Timer module.

•

0 = Quad Timer module clock rate equals system clock rate, to a maximum 32 MHz (default)

•

1 = Quad Timer module clock rate equals three times sytem clock rate, to a maximum 96 MHz

Base + $B

Read

TCR

PCR

CFG_

CFG_A5

CFG_A4

Write

RESET

00000000

0000

GPIOB_PEREN Register

GPIO Controlled

I/O Pad Control

SIM_GPS Register

Quad Timer Controlled

SCI Controlled

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