ADT7490ARQZ-R7 datasheet(70/75 Pages) ONSEMI

70 / 75 page

ADT7490

http://onsemi.com

Table 81. Register 0x88 — PECI Configuration Register 2 (Power−On Default = 0x00)

Bit No.

Mnemonic

R/W (Note 1)

Description

[2:0]

RES

R/W

Reserved.

[3]

DOM3

R/W

CPU domain count information. Set to 0 indicates that CPU 4 associated with the PECI3

reading has a single domain (default). Set to 1 indicates that the system CPU4 contains two

domains.

[4]

DOM2

R/W

CPU domain count information. Set to 0 indicates that CPU 3 associated with the PECI2

reading has a single domain (default). Set to 1 indicates that the system CPU3 contains two

domains.

[5]

DOM1

R/W

CPU domain count information. Set to 0 indicates that CPU 2 associated with the PECI1

reading has a single domain (default). Set to 1 indicates that the system CPU2 contains two

domains.

[7:6]

#CPU

R/W

CPU count. These bits indicate the number of CPUs in the system, which provide PECI

thermal information to the ADT7490.

00 = 1 CPU (default); indicates that PECI0 data is available from CPU 1 at Address 0x30.

01 = 2 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30 and PECI1

data is available from CPU 2 at Address 0x31.

10 = 3 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data

is available from CPU 2 at Address 0x31 and PECI2 data is available from CPU 3 at Address

0x32.

11 = 4 CPUs; indicates that PECI0 data is available from CPU1 at Address 0x30, PECI1 data

is available from CPU 2 at Address 0x31, PECI2 data is available from CPU 3 at Address

0x32 and PECI3 data is available from CPU 4 at Address 0x33.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

Table 82. Operating Point Registers (Note 1 and 2)

R/W (Note 3)

Description

Power−On Default

0x8A

R/W

PECI operating point register.

0xFB

0x8B

R/W

Remote 1 operating point register (default = 100°C).

0x64

0x8C

R/W

Local temperature operating point register (default = 100°C).

0x64

0x8D

R/W

Remote 2 operating point register (default = 100°C).

0x64

1. These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled.

2. The fans being controlled are adjusted to maintain temperature about an operating point.

3. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

ADT7490ARQZ-R7 bảng dữ liệu(PDF) 70 Page - ON Semiconductor

ADT7490ARQZ-R7 bảng dữ liệu(HTML) 70 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

bảng dữ liệu tải về

Link URL