ADT7490ARQZ-R7 datasheet(53/75 Pages) ONSEMI

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ADT7490

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Table 36. TCONTROL Limit Register (Power−On Default = 0x00) (Note 1)

R/W (Note 2)

Description

0x3D

R/W

PECI TCONTROL limit.

1. If any PECI reading exceeds the TCONTROL limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism

incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software

or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below TCONTROL

limit − hysteresis.

2. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any further attempts to write to this register

have no effect.

Table 37. Register 0x3F — Version Register

Bit No.

Mnemonic

R/W

Description

[1:0]

REV[1:0]

Read−only

These two bits indicate the ADT7490 silicon revision number. 0x00 indicates Revision 0,

0x01 indicates Revision 1, and so on. 0x11 indicates that further revision information can be

found in the “Extended Revision” register (0x12). The revision number is then found by

adding 0x11 to the contents of the extended revision register.

[2]

PECI

Read−only

This bit is set to 1 indicating that the ADT7490 supports the PECI interface.

[3]

4−Wire

Read−only

This bit is set to 1 indicating that the ADT7490 may be configured to drive 4−wire fans using

high frequency PWM.

[7:4]

VER[3:0]

Read−only

These bits indicate the version number of the device. This is set to 6, indicating that the

ADT7490 is part of the Heceta 6 ASIC family.

Table 38. Register 0x40 — Configuration Register 1 (Power−On Default = 0x04)

Bit No.

Mnemonic

R/W (Note 1)

Description

[0]

STRT

(Notes 2, 3)

R/W

Logic 1 enables monitoring and PWM control outputs based on the limit settings

programmed. Logic 0 disables monitoring and PWM control is based on the default powerup

limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written

to this bit and the default settings are enabled. This bit does not become locked once Bit 1

(LOCK bit) is set.

[1]

LOCK

Write once

Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers

become read−only and cannot be modified until the ADT7490 is powered down and powered

up again. This prevents rogue programs such as viruses from modifying critical system limit

settings. (Lockable.)

[2]

RDY

Read−only

This bit is set to 1 by the ADT7490 to indicate that the device is fully powered up and ready

to begin system monitoring.

[3]

Fan Boost

R/W

When this bit is set to Logic 1, all PWM outputs go to 100% regardless of other fan speed

configurations and automatic fan speed control settings. When this bit is set to 0, the fan

speed control returns to the fan speed setting calculated by the preprogrammed fan speed

control settings. This bit remains writable after the LOCK bit is set.

[4]

PECI

Monitor

R/W

Set this bit to Logic 1 to enable CPU thermal monitoring via PECI interface. This bit becomes

read−only when the LOCK bit is set.

[5]

THERM in

Manual

R/W

When this bit is set to Logic 1, THERM is enabled so that the fans go to 100% duty cycle on a

THERM or TCONTROL assertion overriding any other fan setting, even when the PWMs are

configured for manual mode, or disabled. This bit becomes read−only when the LOCK bit is set.

[7:6]

RES

Read−only

Reserved.

1. This register becomes read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to this

2. Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after the LOCK bit is set.

3. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.

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