ADT7490ARQZ-R7 datasheet(56/75 Pages) ONSEMI

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ADT7490

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Table 44. Fan Tachometer Limit Registers (Note 1)

R/W

Description

Power−On Default

0x34

R/W

PECI low limit.

0x81

0x54

R/W

TACH1 minimum low byte.

0xFF

0x55

R/W

TACH1 minimum high byte/single−channel ADC channel select.

0xFF

0x56

R/W

TACH2 minimum low byte.

0xFF

0x57

R/W

TACH2 minimum high byte.

0xFF

0x58

R/W

TACH3 minimum low byte.

0xFF

0x59

R/W

TACH3 minimum high byte.

0xFF

0x5A

R/W

TACH4 minimum low byte.

0xFF

0x5B

R/W

TACH4 minimum high byte.

0xFF

1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set

in Interrupt Status Register 2 (0x42) to indicate fan failure. Setting the Configuration Register 1 (0x40) LOCK bit has no effect on these

registers.

Table 45. Register 0x55 — TACH1 Minimum High Byte (Power−On Default = 0xFF)

Bit No.

Mnemonic

R/W

Description

[3:0]

Reserved

Read−only

When Bit 6 of Configuration 2 Register (0x73) is set (single−channel ADC mode), these bits

are reserved. Otherwise, these bits represent Bits [3:0] of the TACH1 minimum high byte.

[7:4]

SCADC

R/W

When Bit 6 of Configuration 2 Register (0x73) is set (single−channel ADC mode), these bits

are used to select the only channel from which the ADC will take measurements. Otherwise,

these bits represent Bits [7:4] of the TACH1 minimum high byte.

Bit Code

Single−Channel Select

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

+2.5 VIN

VCCP

VCC

+5 VIN

+12 VIN

Remote 1 temperature

Local temperature

Remote 2 temperature

VTT

IMON

Table 46. PWM Configuration Registers

R/W (Note 1)

Description

Power−On Default

0x34

R/W

PECI low limit.

0x81

0x5C

R/W

PWM1 configuration.

0x62

0x5D

R/W

PWM2 configuration.

0x62

0x5E

R/W

PWM3 configuration.

0x62

1. These registers become read-only when the Configuration Register 1 (0x40) LOCK bit is set to 1. Any subsequent attempts to write to

these registers fail.

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