IP4778CZ38_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 12 February 2009

13 of 26

NXP Semiconductors

IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10. Application information

10.1 TMDS

To protect the TMDS lines and also to comply with the impedance requirements of the

HDMI specification, the IP4778CZ38 provides ESD protection with a low capacitive load.

The dominant value for the TMDS line impedance is the capacitive load to ground. The

IP4778CZ38 has a capacitive load of only 0.7 pF.

10.2 DDC circuit

The DDC-bus circuit contains full capacitive decoupling between the HDMI connector and

the DDC-bus lines on the PCB. The capacitive decoupling ensures that the maximum

capacitive load is within the 50 pF maximum of the HDMI specification.

The slew rate accelerator supports high capacitive load on the HDMI cable side. Various

HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a

capacitive load of up to 6 nF.

The slew rate accelerator boosts the DDC signal independent of which side of the bus is

releasing the signal. The DDC module provides a level shifting and a multiplex option

which is enabled by the ENABLE signal.

Fig 6.

ESD protection of TMDS lines

001aag039

TMDS_D2+

TMDS_D1+

TMDS_D0+

TMDS_BIAS

TMDS_GND

TMDS_CLK+

TMDS_CLK

−

TMDS_D0

−

TMDS_D1

−

TMDS_D2

−

a. DDC clock

b. DDC data

Fig 7.

DDC circuit

001aag040

SLEW

RATE

ACCELERATOR

ENABLE

DDC_CLK_IN

TMDS_BIAS

DDC_CLK_OUT

001aag041

SLEW

RATE

ACCELERATOR

ENABLE

DDC_DAT_IN

TMDS_BIAS

DDC_DAT_OUT