IP4778CZ38SLASHV datasheet(8/26 Pages) NXP

8 / 26 page

IP4778CZ38_2

Product data sheet

Rev. 02 — 12 February 2009

8 of 26

NXP Semiconductors

IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

Board side: pins DDC_CLK_OUT and DDC_DAT_OUT

Used as input

VIH

HIGH-level input voltage

0.7

× V

CC(3V3)

5.5

VIL

LOW-level input voltage

−0.5

0.3

× V

CC(3V3)

IIL

LOW-level input current

VI = 0.2 V

µA

VIK

input clamping voltage

Ii = −18 mA

−1.2

ILI

input leakage current

VI = 3.6 V

±1

µA

input capacitance

VI = 3 V or 0 V

VCC(3V3) = 3.3 V

VCC(3V3) = 3.0 V

Used as output

VOL

LOW-level output voltage

IOL = 100 µA or 6 mA

200 -

IOH

HIGH-level output current

VO = 3.6 V

µA

output capacitance

VI = 3 V or 0 V

VCC(3V3) = 3.3 V

VCC(3V3) = 3.0 V

Connector side: pins DDC_CLK_IN and DDC_DAT_IN

Used as input

VIH

HIGH-level input voltage

410 -

VIL

LOW-level input voltage

400 -

IIL

LOW-level input current

DDC_DAT_OUT,

DDC_CLK_OUT, VI = 0.2 V

µA

VIK

input clamping voltage

II = −18 mA

−1.2

ILI

input leakage current

VI = 3.6 V

±1

µA

input capacitance

VI = 3 V or 0 V

VCC(3V3) = 3.3 V

VCC(3V3) = 3.0 V

Used as output

VOL

LOW-level output voltage

IOL = 100 µA or 3 mA

700 -

IOH

HIGH-level output current

VO = 3.6 V

µA

output capacitance

VI = 3 V or 0 V

VCC(3V3) = 3.3 V

VCC(3V3) = 3.0 V

Table 5.

DDC circuit …continued

VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb =25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

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