ICS842S104 datasheet(8/21 Pages) IDT

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ICS842S104CG REVISION A MARCH 17, 2010

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 5. Crystal Characteristics

NOTE: Characterized using an 18pF parallel resonant crystal.

AC Electrical Characteristics

Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High

Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the

PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

MHz

Equivalent Series Resistance (ESR)

Ω

Shunt Capacitance

7pF

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

FOUTCTL = 0

100

MHz

FOUTCTL = 1

200

fref

Reference frequency

MHz

tREFCLK_HF_RMS Phase Jitter RMS; NOTE 1, 2

ƒ= 200MHz,

25MHz crystal input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

0.95

tREFCLK_LF_RMS Phase Jitter RMS; NOTE 1

ƒ= 200MHz,

25MHz crystal input

Low Band: 10kHz - 1.5MHz

0.31

tsk(o)

Output Skew; NOTE 2, 3

tjit(Ø)

Phase Jitter, RMS (Random)

200MHz, Integration Range:

12kHz – 20MHz

1.27

tjit(cc)

Cycle-to-Cycle Jitter

PLL Mode

PLL Lock Time

odc

Output Duty Cycle

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