ICS842S104 datasheet(4/21 Pages) IDT

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ICS842S104CG REVISION A MARCH 17, 2010

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 3B. Block Read and Block Write Protocol

Table 3C. Byte Read and Byte Write Protocol

Bit

Description = Block Write

Bit

Description = Block Read

1Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

9Write

Acknowledge from slave

11:18

Command Code - 8 bits

11:18

Command Code - 8 bits

Acknowledge from slave

20:27

Byte Count - 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address - 7 bits

29:36

Data byte 1 - 8 bits

Read = 1

Acknowledge from slave

38:45

Data byte 2 - 8 bits

30:37

Byte Count from slave - 8 bits

Acknowledge from slave

Acknowledge

Data Byte/Slave Acknowledges

39:46

Data Byte 1 from slave - 8 bits

Data Byte N - 8 bits

Acknowledge

Acknowledge from slave

48:55

Data Byte 2 from slave - 8 bits

Stop

Acknowledge

Data Bytes from Slave/Acknowledge

Data Byte N from slave - 8 bits

Not Acknowledge

Bit

Description = Byte Write

Bit

Description = Byte Read

Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits

11:18

Command Code - 8 bits

Acknowledge from slave

20:27

Data Byte - 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address - 7 bits

Stop

Read

Acknowledge from slave

30:37

Data from slave - 8 bits

Not Acknowledge

Stop

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